1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method of the semiconductor device. In particular, the present invention relates to a GaN (gallium nitride) related high power semiconductor device for obtaining stabilized high frequency performance, and a fabrication method of the semiconductor device.
2. Description of the Related Art
It is known that FETs (Field Effect Transistors) using a GaN (gallium nitride) related semiconductor have a large amount of current collapse and have a large amount of leakage current. As one of the cause, crystal dislocations and crystal defects in an epitaxial crystal are mentioned.
Since the crystal defect causes fundamental performance degradation, such as an amount of increase of the leakage current and occurring of the current collapse phenomenon, it is dramatically important to obtain an epitaxial layer with little crystal defects.
In order to suppress the amount of crystal dislocations and the amount of crystal defects, a method of inserting an AlGaN (aluminum gallium nitride) layer and an AlN (aluminum nitride) layer into the GaN layer is known.
As shown in FIG. 1, a conventional semiconductor device includes, for example, a substrate 10 composed of SiC, a GaN layer 120 placed on the substrate 10, an AlN layer or an AlGaN layer 16 placed on the GaN layer 120, a GaN layer 200 placed on the AlN layer or the AlGaN layer 16, a AlGaN layer 22 placed on the GaN layer 200, and a gate electrode 26, a source electrode 24, and a drain electrode 28 which are placed on the AlGaN layer 22.
However, since GaN and AlGaN or AlN have a large amount of lattice constant difference, the amount of electric charges is induced between the GaN layer and the AlGaN layer by piezo polarization effect. Therefore, there was a problem that the amount of electric charges induced in the GaN layer degrades the high frequency performance of the semiconductor device extremely.
For example, in FIG. 1, since the GaN layer 120 and the AlN layer or AlGaN layer 16 have a large amount of lattice constant difference, the amount of electric charges is induced between the GaN layer 120 and the AlN layer or the AlGaN layer 16 by piezo polarization effect. Therefore, there is a problem that the amount of electric charges induced in the GaN layer 120 degrades the high frequency characteristics of the semiconductor device extremely. Similarly, since the GaN layer 200 and the AlN layer or AlGaN layer 16 have a large amount of lattice constant difference, the amount of electric charges is induced between the GaN layer 200 and the AlN layer or AlGaN layer 16 by piezo polarization effect. Therefore, there is a problem that the amount of electric charges induced in the GaN layer 200 degrades the high frequency characteristics of a semiconductor device extremely.
The amount of electric charges induced by such piezo polarization effect becomes the cause of increasing the conductivity of the GaN layer 120 or 200, increasing the leakage current between the gate electrode 26 and the source electrode 24 or between the gate electrode 26 and the drain electrodes 28, and reducing power amplification gain of the semiconductor device.
It is already disclosed about a field effect transistor using a GaN related semiconductor which can form a gate size in 0.1 micrometer class and does not occurs the leakage current between the gate electrode and the source electrode, or between the gate electrode and drain inter-electrode, and a fabrication method of the field effect transistor (for example, refer to Patent Document 1). In the Patent Document 1, gate leakage current is reduced by using a field effect transistor which has a gate electrode whose sectional shape is T shape.
Moreover, it is already disclosed about a high resistivity III group nitride semiconductor crystal, a high resistivity group III nitride semiconductor substrate, a semiconductor device and a fabrication method of the high resistivity III group nitride semiconductor crystal (for example, refer to Patent Document 2). In the Patent Document 2, a group III nitride semiconductor crystal in which Fe is doped, for example as transition metals, the group III nitride semiconductor crystal being an Fe doped GaN layer whose value of the concentrations of Gallium atom vacancy is less than or equal to 1×1016 cm−3, is disclosed. The value of the concentrations of the Ferrum atoms in the Fe dope GaN layer is 5×1017 cm−3 to 5×1020 cm−3. Moreover, it is disclosed also about a semiconductor device, which has a semiconductor layer formed on the group III nitride semiconductor substrate composed of the above-mentioned Fe dope GaN layer.
Moreover, it is already disclosed also about a semiconductor element which can perform multilayer formation of a plurality of nitride based compound semiconductor layers, which have a difference of a lattice constant more than a predetermined value, in the effective crystalline state, and can control propagation of penetration dislocation to an epitaxial growth direction (for example, refer to Patent Document 3). However, in the Patent Document 3, it is not disclosed about Fe dope GaN layer for obtaining the high resistivity group III nitride semiconductor crystal.
Patent Document 1:
Japanese Patent Application Laying-Open Publication No. 2002-141499 (Pages 3 to 4 and FIG. 1)
Patent Document 2:
Japanese Patent Application Laying-Open Publication No. 2007-184379 (Pages 6 to 7, FIG. 4 and FIG. 5)
Patent Document 3:
Japanese Patent Application Laying-Open Publication No. 2007-221001 (FIG. 1, FIG. 7, and FIG. 10)